1. Field of the Invention
The invention relates to a decoder which decodes the conduction state of memory cells in a memory array, and particularly, to an improvement that reduces the static power consumption of the decoder. The invention also relates to a programmable logic device ("PLD") employing the improved decoder to initialize logic arrays of the PLD during start up of the PLD.
2. Description of the Prior Art
Memories in electronic devices include an array of memory cells arranged in rows and columns and various peripheral circuits which address individual cells in the array to program a cell, erase a cell and read the programmed state of a cell. FIG. 1A illustrates one type of electrically erasable programmable read only memory (EEPROM) cell 10 A having a CMOS memory transistor 1 and an access transistor 15. The memory transistor 1 has a drain D, a source S, a floating gate FG, and a control gate CG that is coupled to a bit line BL. As is well known in the art, the cell 10 can be programmed, by applying appropriate voltages to the drain, source and control gate, so that the channel 11 of the device is conductive (representing a first logic state) or non-conductive (representing the other logic state). The non-conductive state is achieved by charging the floating gate with negative charge carriers. The conductive state is obtained when the negative charge carriers are removed from the floating gate. The access transistor 15 has a control gate coupled to a word line WL which receives a read address (R.sub.ADD) signal. The access transistor is selectively turned on and off by the R.sub.ADD signal to allow the memory cell to be read, programmed or erased. The cell 10 is known as a full-featured EEPROM since the access transistor 1 allows each byte or memory transistor 1 to be individually addressed. Standard and flash EEPROM's do not have an access transistor associated with each memory transistor, and must be erased in groups.
A sense amplifier 20 selectively coupled to the bit line allows the state of the cell 10 A to be read. During a read operation, the access transistor 15 is rendered conductive to couple the source of the memory transistor 1 to device ground. A low DC voltage is applied to the bit line BL by the sense amplifier or a separate load circuit. The sense amplifier 20 determines the logic level of the cell by sensing the level of current flowing through the channel of the cell and comparing to a reference current. A conductive cell will have a current flow higher than the reference current and will be detected as a first logic state. A non-conductive cell will have little or no current and will be detected as the other logic state. Whether a conductive cell is considered logic high or logic low is arbitrary and depends on the application. Details of programming and erasing the cell of FIG. 1 A are known, among others, from U.S. Pat. No. 5,687,352.
FIG. 1B illustrates a second type of memory cell 10B which isolates the read operation from the programming operation using an additional high voltage NMOS (HVNMOS) transistor 17. Such a cell is bulk erased by, for example, making it non-conductive by applying the following signals: CG=V.sub.pp (12 v); P.sub.ADD =logic "1" (5 V); DATA=logic "0" (Gnd); R.sub.ADD ="0". This initially removes any charge on the floating gate FG of transistor 1. When CG is subsequently coupled to ground, however, the floating gate acquires a negative charge, rendering transistor 1 non-conductive. The cell is programmed by coupling CG to ground, applying V.sub.pp (12 v) to P.sub.ADD and then applying a signal 0 V or V.sub.pp as the DATA signal. If DATA=V.sub.pp the transistor 1 is rendered conductive. If DATA=0 V, then the transistor is not conductive.
A drawback of conventional sense amplifiers is that a static DC voltage is made available to the bit lines during the read operation. Since a memory array includes a large plurality of cells, when the decoder is used to read the state of the memory, for example during initialization of a battery operated electronic device, more than an inconsequential amount of power is used. This is of a particular concern as the market for low voltage devices increases. For example, Philips Semiconductors markets a line of low voltage complex PLD's ("CPLDs") under the brand name COOLRUNNER.TM.. These devices operate nominally at 3 V, after initialization of the logic arrays from a non-volatile memory. However, during initialization of the logic arrays, the static DC power drawn from the sense amplifier is more than that used by the CPLD during normal operation. The power draw during the initialization is inconsistent with the desired low power, low voltage operation of the device.